A little electronics lab

Some things I've built. Some things I'm still trying to understand.
Figured it would be nice to put a few of them here.

Making it find a square root

This is the microcontroller from my VLSI project. No multiply or divide instructions. Just shifts, subtraction, and a fair amount of moving bytes around.

A functional browser model of the processor, with a corrected square-root ROM based on the project's C code.

One state every quarter second.

Enable JavaScript to run the processor. The code and explanation are below.

Result: not run yet.

I1 Address
I2 Fetch
I3 Decode
I4–I10 Execute

PC starts at 04, the calculation interrupt vector.

0 state steps · 0 instructions · 0 / 8 bit pairs

The program

Start

Inside the machine

PC: 04
MAR: 00
IR: 00
ACC: 00
F: 0
Z: 1

Registers are hexadecimal. F is carry/borrow; Z means ACC is zero.

Working input (A): 123
Remainder (X): 0
Trial divisor (Y): 0
Root (B): 0

Working values above are decimal.

Control signals

Not started.

Data bus: idle.

The eight iterations

Pair	Bits	Trial	Remainder	Root

No pairs processed yet.

The code, before the assembly

The input is read two bits at a time. Try a subtraction, keep it if it fits, then append a bit to the root. Eight rounds for a 16-bit input.

uint16_t rootf(uint16_t input) {
    uint16_t accumulator = 0;
    uint16_t extracted = 0;
    int16_t bitDepth = 7;

    while (bitDepth >= 0) {
        extracted = (extracted << 2)
                  | ((input >> (bitDepth * 2)) & 0b011);
        uint16_t sub = (accumulator << 2) | 1;

        if (extracted >= sub) {
            extracted -= sub;
            accumulator = (accumulator << 1) | 1;
        } else {
            accumulator <<= 1;
        }
        bitDepth--;
    }
    return accumulator;
}

Original C file · The ROM running here

About this version

The instruction set, accumulator flags and I1–I10 controller states follow the project's VHDL. These are sequential controller states, not a pipeline. The browser starts after the ROM has been loaded into RAM, with the input bytes already set, at the calculation interrupt vector.

The ROM program here is a corrected translation of square.c. The checked-in ROM gave 11 for 123, but 116 for 65535 in an instruction-level check. This version keeps both bytes of the remainder and trial divisor, and checks subtraction borrow. It has been tested for every input from 0 to 65535.

This is a functional model, not an electrical simulation. The board's button debouncing, ROM-copy startup, RAM clock edges and seven-segment wiring are left out. RAM writes update the data byte; undriven upper bits are not simulated. The downloadable ROM hasn't been tested on an FPGA.

Original project files

Also on the desk

ApocaCore — a processor simulator. Started this to understand RISC-V a bit better.

Square root in hardware — shifts, subtraction, and a result slowly taking shape.

For now these go to the code. I'll bring more things here as I go.